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?2008 scillc. all rights reserved. publication order number: june 2008 ? rev. 16 belasigna200/d belasigna 200 1.0 general description belasigna 200 is a high-performance, programmable, mixed-si gnal digital signal processor (dsp) that is based on on semiconductor?s patented second-generation signaklara? technology. this single-chip solution is ideally suited for embedded applic ations where audio performance, low power consumption and miniaturization are critical. belasigna 200 targets a wide variety of digital speech- and audio-centric applications, including : ? communication headsets ? smart phones ? personal digital assistants (pdas) ? hands-free car kits ? bluetooth? wireless technology systems belasigna 200 provides numerous analog and digital interfaces including parallel, serial, synchronous, and asynchronous interfa ces to facilitate the connection with transducers from various applications. belasigna 200 contains two primary processi ng blocks, which all work together to provide a complete audio processing chain. the analog section includes two 16-bit a/d converters and two 16-bit d/ a converters. two on-chip direct digital output stages allow belasigna 200 to drive various output transducers directly , eliminating the need for external power amplifiers. belasigna 200 features internal clock generation and power regulation for excellent noise and power performance. two dsp subsystems operate concurrently: the rcore , which is a fully programmable dsp core, and the weighted overlap-add (wola) filterbank coprocessor, which is a dedicated, configurable processor that executes time-frequency domain transforms and other v ector- based computations. in addition to these processors, there are several other peripherals, which optimize the architecture to au dio processing, such as the onput/out put processor (iop) ? an audio-targeted direct me mory access (dma) processor, which runs in th e background and manages the data flow between the converters and the two processors. the belasigna 200 functional block diagram is shown in figure 1 . figure 1: belasigna 200 functional block diagram
belasigna 200 2.0 key features 2.1 system ? 16-bit programmable fixed-point dsp core ? configurable wola filterbank coproces sor optimized for filterbank calculations ? 12-kword program memory (pram) ? two 4-kword data memories (xram and yram) ? two 384-word dual-port fifo memories ? two 128-word dual-port 18-bit memories dedicated to wola output results ? 576-word memory dedicated to wola gain values, wola windows and other configuration data ? internal oscillator ? operating voltage of 1.8v nominal ? ultra-low power: less than 1mw @ 1.28mhz system clock frequenc y, 1.8v nominal operating volt age, both processors running ? available in a qfn package; other packages available upon request 2.2 rcore dsp ? dual-harvard architecture, 16-bit programmable fixed-point dsp with three execution units ? single-cycle multiply-accumulate (mac) with 40-bit accumulator ? highly parallel instruction set with powerful addressing modes ? flexible address generation (including modulo addressing) for accessing program memory and data memories, plus control and configuration registers ? separate system and user stacks with dedicated stack pointers ? fast normalization and de-normalization operations optimized fo r signal level calculation and block-floating point calculation s ? supports time-domain pre- and post-processing of input data stream and frequency-domain processing of wola output ? master processor for entire system 2.3 wola filterbank coprocessor ? mono and stereo time-frequency transforms providing real or complex data results ? standard library of overlap-add (ola ) and wola filterbank configurations o configurable number of frequency bands o configurable number of frequency bands o configurable oversampling and decimation factors o configurable windows ? low group delay (< 4ms for 16 bands possible) ? fast real and complex gain application for magnitude and phase processing ? block floating-point calculations (4-bit expo nent, 18-bit mantissa) to achieve high fidelity ? maximum digital gain of 90db possible ? high-fidelity time-frequency domain processing ? low-overhead interaction with the rcore through shared memories, control registers and interrupts 2.4 input output processor (iop) ? block-based dma for all audio data provides automatic management of input and output fifos t hat reduces processor overhead ? mono (one in, one out), simple stereo (two in, one out), full stereo (two in, two out) and digital mixed (two in, one out) ope rating modes ? interacts with the rcore through interrupts and shared memories ? normal and smart fifo audio data accessing schemes available rev. 16 | page 2 of 43 | www.onsemi.com
belasigna 200 2.5 input stage ? two separate input channels, each with two multiplexed inputs ? two configurable preamplifiers for im proved input dynamic range matching ? two analog third-order anti-aliasing filters ? two 16-bit oversampling ? a/d converters ? two ninth-order low-delay wave digital filters (wdfs) for decimation and dc removal with configurable digital gains for optima l channel matching 2.6 output stage ? two output channels (full stereo) ? two 16-bit oversampling ? d/a converters ? two line-level analog outputs ? two configurable output attenuators fo r improved output dynamic range matching ? two analog third-order anti-aliasing filters ? two pulse-density modulation (pdm)-based direct digital outputs capable of driving low-impedance loads 2.7 peripherals and interfaces 2.7.1. analog interfaces ? six external low-speed a/d converter (lsad) inputs can be used with analog trimmers (e.g., potentiometers, analog switches, et c.) ? two internal lsad inputs tied directly to ground and supply can be used for supply monitoring 2.7.2. digital interfaces ? 16-pin general- purpose i/o (gpio) interface ? serial peripheral interface (spi) communications port with interface speeds up to 640kbps at 1.28mhz system clock ? pulse-code modulation (p cm) interface for high-b andwidth digital audio i/o ? configurable rs-232 universal asynchronous receiver/transmitter (uart) ? rs-232-based communications port for debugging and in-circuit emulation ? two-wire synchronous serial (twss) interface with speeds up to 100kbps at 1.28mhz system clock and up to 400kbps at higher system clocks (slave mode support only) 2.7.3. system ? integrated watchdog timer ? general-purpose timer ? external clock input division circuitry to support a wide range of external clock speeds rev. 16 | page 3 of 43 | www.onsemi.com
belasigna 200 3.0 belasigna 200 design and layout strategies belasigna 200 is designed to allow both digital and analog processing in a single system. due to the mixed-signal nature of thi s system, the design of the printed circuit bo ard (pcb) layout is critical to maintain the high audio fidelity of belasigna 200. to avoid coupling noise into the audio signal path, keep the digital traces away from the analog traces. to avoid electrical feedback co upling, isolate the input traces from the output traces. 3.1 recommended ground design strategy the ground plane should be partitioned into two: the analog ground plane (agnd) and the digital ground plane (dgnd). these two planes should be connected together at a single point, known as t he star point. the star point should be located at the ground terminal of a capacitor on the out put of the power regulator as illustrated in figure 2 . figure 2: schematic of ground scheme the dgnd plane is used as the ground return for digital circuits and should be placed under digital circuits. the agnd plane should be kept as noise-free as possible. it is used as the ground retu rn for analog circuits and it should surr ound analog components and pins. it should not be connected to or placed under any noisy circuits such as rf chips, switching suppli es or rev. 16 | page 4 of 43 | www.onsemi.com
belasigna 200 digital pads of belasigna 200 itself. analog ground returns a ssociated with the audio output stage should connect back to the s tar point on separate individual traces. for more information on the recommended ground design strategy, see table 1 . in some designs, space constraints may make separate ground planes impractical. in this case a star configuration strategy shou ld be used. each analog ground return should connec t to the star point with separate traces. 3.2 internal power supplies power management circuitry in belasigna 200 generates separate digital (vddc) and analog (vreg, vdbl) regulated supplies. each supply requires an external decoupling capacitor, even if the su pply is not used externally. decoupling capacitors should be pl aced as close as possible to the power pads. further details are provided in table 1 . non-critical signals are outlined in table 2 . table 1: critical signal pin name description routing guideline vbat power supply place 1 f (min) decoupling capacitor close to pin. connect negative terminal of capacitor to dgnd plane. vreg, vdbl internal regulator for analog sections place separate 1 f decoupling capacitors clos e to each pin. connect negative capacitor terminal to agnd. keep away from digital traces and output traces. vreg may be used to generate microphone bias. vdbl shall not be used to supply external circuitry. agnd analog ground return connect to agnd plane. vddc internal regulator for digital sections place 10 f decoupling capacitor close to pin. connect negative terminal of capacitor to dgnd. should be connected to vddo pins and to eeprom power. gndo, gndc digital ground return (pads and core) connect to digital ground. ai0, ai1 / lout, ai2, ai3 microphone inputs keep as short as possible. keep away from all digital traces and audio outputs. avoid routing in parallel with other traces. connect unused inputs to agnd. air input stage reference voltage connect to agnd. if no analog ground plane, should share trace with microphone grounds to star point. ao0, ao1 analog audio output keep away from microphone inputs. rcvr0+, rcvr0-, rcvr1+, rcvr1- direct digital audio output keep away from analog traces, pa rticularly microphone inputs. corresponding traces should be of approximately the same length. aor output stage reference voltage connect to star point. share trace with power amplifier (if present). rcvrgnd output stage ground return connect to star point. ext_clk external clock input / internal clock output minimize trace length. keep away from analog signals. if possible, surround with digital ground. ai_rc infrared receiver input if used, minimize trace length to photodiode. rev. 16 | page 5 of 43 | www.onsemi.com
belasigna 200 table 2: non-critical signal pin name description routing guideline cap0, cap1 internal charge pump - capacitor connection place 100nf capa citor close to pins debug_tx, debug_rx debug port not critical connect to test points twss_sda, twss_clk twss port not critical gpio[14..0] general-purpose i/o not critical gpio[15] general-purpose i/o determines voltage mode during boot. for 1.8v operation, should be connected to dgnd not critical uart_rx, uart_tx general-purpose uart not critical pcm_frame, pcm_clk, pcm_out, pcm_in pulse code modulation port not critical i2s_ina, i2s_ind, i2s_fa, i2s_fd, i2s_outa, i2s_outd philips i2s compatible port not critical dclk programmable clock output not critical if used, keep away from analog inputs/outputs lsad[5..0] low-speed a/d converters not critical spi_clk, spi_cs, spi_seri, spi_sero serial peripheral interface port connect to eeprom not critical 3.3 audio inputs the audio input traces should be as short as possible. the inpu t impedance of each audio input pad (e.g., ai0, ai1, etc.,) is h igh (approximately 500k ? ); therefore a 10nf capacitor is sufficient to decouple the dc bias 1 . keep audio input traces strictly away from output traces. microphone ground terminals should be connected to th e agnd plane (if present) or share a trace with the input g round reference voltage pin (air) to the star point. analog and digital outputs must be k ept away from microphone inputs. 3.4 audio outputs the audio output traces should be as short as possible. if the direct digital output is used, the trace l ength of rcvrx+ and rc vrx- should be approximately the same to provide matched impedances. if the analog audio output is used, the ground return for the external power amplifier should share a trace with the out put ground reference voltage pin (aor) to the star point. 1 the capacitor and the internal resistance form a first-order anal og high pass filter whose cutoff frequency can be calculated by f 3db (hz) = 1/(r ? c ?2s ), which results with ~30hz for 10nf capacitor. rev. 16 | page 6 of 43 | www.onsemi.com
belasigna 200 4.0 mechanical and environmental information belasigna 200 is available in two packages: ? the qfn package measures 8x8mm, has easy -to-probe signals an d all i/o available. ? the csp package is the ultra-miniature opt ion, measuring only 2.3x3.7m m; this package has reduced i/o and flexibility, but still meets a wide range of application needs. 4.1 qfn package option 4.1.1. qfn mechanical information figure 3: qfn mechanical drawings rev. 16 | page 7 of 43 | www.onsemi.com
belasigna 200 4.1.2. qfn pad out pad # pad name pad function i/o u/d 1 cap0 charge pump capacitor pin 0 n/a n/a 2 vdbl double voltage o n/a 3 a|0 audio signal input to adc0 i n/a 4 a|1/lout audio signal input to adc0/line level output signal from preamp 0 i/o n/a 5 a|r reference voltage for microphone n/a n/a 6 a|2 audio signal input to adc1 i n/a 7 a|3 audio signal input to adc1 i n/a 8 vreg regulated voltage for microphone bias o n/a 9 agnd analog ground n/a n/a 10 ai_rc remote control input i n/a 11 aor reference voltage for dac n/a n/a 12 ao1/rcvr1- audio signal output from dac1/output from direct digital drive 1- o n/a 13 ao0/rcvr1+ audio signal output from dac0/output from direct digital drive 1+ o n/a pad # pad name pad function i/o u/d 14 vbat positive power supply i n/a 15 rcvr0- output from direct digital drive 0 o n/a 16 rcvr0+ output from direct digital drive 0 o n/a 17 rcvrgnd receiver return current n/a n/a 18 gpio[3]/ nclk_div_reset/i2s_fa general-purpose i/o/clock di vider reset/i2s interface analog blocks frame output i/o u 19 gpio[2]/i2s_ina general-purpose i/o/i2s interface analog blocks input i/o u 20 gpio[1]/i2s_ind general-purpose i/o/i2 s interface analog blocks input i/o u 21 gpio[0]/i2s_fd general-purpose i/o/i2s interface digital blocks frame i/o u 22 vddo digital pads supply input i n/a 23 gndo digital pads ground n/a n/a 24 ext_clk external clock input/internal clock output i/o u 25 debug_rx debug port receive i u 26 debug_tx debut port transmit o u pad # pad name pad function i/o u/d 27 reserved n/a n/a 28 twss_sda twss data i/o u 29 twss_clk twss clock i u 30 gndc core logic ground n/a n/a 31 vddc core logic, eeprom and pad supply output o n/a 32 spi_sero serial peripheral interface serial data out i/o d 33 spi_seri serial peripheral interface serial data in i u 34 spi_cs serial peripheral interface chip select i/o d 35 spi_clk serial peripheral interface clock i/o n/a 36 gpio[15] general-purpose i/o i/o u 37 gpio[14]/pcm_frame general-purpos e i/o/pcm interface frame i/o u 38 gpio[13]/pcm_out general-purpose i/o/pcm interface output i/o u 39 gpio[12]/pcm_in general-purpose i/o/pcm interface input i/o u pad # pad name pad function i/o u/d 40 n/c no connection n/a n/a 41 n/c no connection n/a n/a 42 gpio[11]/pcm_clk general-purpos e i/o/pcm interface clock i/o u 43 gndo digital pads ground n/a n/a 44 vddo digital pads supply input i n/a 45 gpio[10]/dclk general-purpose i/o/class d receiver clock i/o u 46 lsad[5]/gpio[9]/uart_rx low-speed a/d/general-purpose i/o/general-purpose uart receive i/o u 47 lsad[4]/gpio[8]/uart_tx low-speed a/d input/general-purpose i/o/general- purpose uart transmit i/o u 48 lsad[3]/gpio[7] low-speed a/d input/general purpose i/p i/o u 49 lsad[2]/gpio[6] low-speed a/d input/general purpose i/p i/o u 50 lsad[1]/gpio[5]/i2s_outa low-speed a/d inputs/general-purpose i/o/i2s interface analog blocks output i/o u 51 lsad[0]/gpio[4]/i2s_outd low-speed a/d inputs/general-purpose i/o/i2s interface analog blocks output i/o u 52 cap1 charge pump capacitor pin 1 n/a n/a rev. 16 | page 8 of 43 | www.onsemi.com
belasigna 200 4.1.3. qfn environmental characteristics all parts supplied against this specific ation have been qualified as follows: table 3: environmental characteristics characteristics packaging level moisture sensitivity level jedec level 3 30c / 60% rh for 192 hours pressure cooker test (pct) 121c / 100% rh / 2 atm for 168 hours thermal cycling test (tct) -65c to 150c for 1000 cycles highly accelerated stress test (hast) 130c / 85% rh for 100 hours high temperature stress test (htst) 150c for 1000 hours board level temperature -40c to 125c for 2500 cycles with no failures drop 1m height with no failures bending 1mm deflection / 2hz 4.1.4. qfn carrier information on semiconductor offers tape and reel packing for belasigna 20 0 qfn packages. the packing consists of a pocketed carrier tape, a cover tape, and a molded anti-static polystyrene reel. the carrier and cover tape create an esd safe environment, protecting the qfns from physical and electro-static damage during shipping and handling. reel top view reel diameter: 13 inches quantity per reel: 500 pieces date codes: max. of two date codes can be combined into one reel figure 4: qfn reel format protective retainer mfg. packing label carrier tape lokreel esd label q.a. inspection passed stam p rev. 16 | page 9 of 43 | www.onsemi.com
belasigna 200 all dimensions in millimeters ao = 8.3 mm bo = 8.3 mm ko = 2.0 mm k1 = 1.0 mm figure 5: qfn tape dimensions notes: 1. 10 sprocket hole pitch cumulative tolerance 0.02. 2. camber not to exceed 1 mm in 100 mm. 3. material: ps+c.2. 4. ao and bo measured on a plane 0.3 mm above the bottom of the pocket. 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. pocket position relati ve to sprocket hole measured as true position of pocket, not pocket hole. . pocket position relati ve to sprocket hole measured as true position of pocket, not pocket hole. figure 6: qfn orientation in tape rev. 16 | page 10 of 43 | www.onsemi.com
belasigna 200 4.2 csp package option 4.2.1. csp mechanical information figure 7: csp mechanical drawings rev. 16 | page 11 of 43 | www.onsemi.com
belasigna 200 4.2.2. csp pad out table 4: pad out (advance information) pad index pad name pad function i/o u/d b2 cap0 charge pump capacitor pin 0 n/a n/a a2 cap1 charge pump capacitor pin 1 n/a n/a a1 vdbl double voltage o n/a c3 vreg regulated voltage for microphone bias o n/a b3 a|0 audio signal input to adc0 i n/a b1 a|1/lout audio signal input to adc0/line level output signal from preamp 0 i/o n/a c2 a|2 audio signal input to adc1 i n/a c1 a|3 audio signal input to adc1 i n/a b4 a|r reference voltage for microphone n/a n/a c4 agnd analog ground n/a n/a d1 aor reference voltage for dac n/a n/a e1 ao1/rcvr1- audio signal output from dac1/output from direct digital drive 1- o n/a d2 ao0/rcvr1+ audio signal output from dac0/output from direct digital drive 1+ o n/a d3 rcvr0- output from direct digital drive 0 o n/a e3 rcvr0+ output from direct digital drive 0 o n/a d4 rcvrgnd receiver return current n/a n/a e2 vbat positive power supply i n/a e5 vdd core logic, eeprom and pad supply i n/a a6 gndo digital pads ground n/a n/a e6 gndc core logic and pads ground n/a n/a d6 ext_clk external clock input/internal clock output i/o u e7 debug_rx debug port receive i u d7 debug_tx debut port transmit o u e8 twss_sda twss data i/o u d8 twss_clk twss clock i u c8 spi_sero serial peripheral interface serial data out i/o d c7 spi_seri serial peripheral interface serial data in i u b8 spi_cs serial peripheral interface chip select i/o d c6 spi_clk serial peripheral interface clock i/o n/a a8 gpio[14]/pcm_frame general-purpose i/o/pcm interface frame i/o u b7 gpio[13]/pcm_out general-purpose i/o/pcm interface output i/o u a7 gpio[12]/pcm_in general-purpose i/o/pcm interface input i/o u b6 gpio[11]/pcm_clk general-purpos e i/o/pcm interface clock i/o u a5 gpio[10]/dclk general-purpose i/o/class d receiver clock i/o u b5 lsad[5]/gpio[9]/uart_rx low-speed a/d/general-purpose i/o/general-purpose uart receive i/o u a4 lsad[4]/gpio[8]/uart_tx low-speed a/d input/general-purpose i/o/general-purpose uart transmit i/o u c5 lsad[3]/gpio[7] low-speed a/d input/general purpose i/p i/o u a3 lsad[1]/gpio[5]/i2s_out a low-speed a/d inputs/general-purpose i/o/i2s interface analog blocks output i/o u d5 lsad[0]/gpio[4]/i2s_out d low-speed a/d inputs/general-purpose i/o/i2s interface analog blocks output i/o u e4 gpio[3]/ nclk_div_reset/i2s_fa general-purpose i/o/clock divider re set/i2s interface analog blocks frame output i/o u rev. 16 | page 12 of 43 | www.onsemi.com
belasigna 200 4.2.3. csp environmental characteristics all parts supplied against this specific ation have been qualified as follows: table 5: packaging level moisture sensitivity level (msl) jedec level 3 30c / 60% rh for 192 hours pressure cooker test (pct) 121c / 100% rh / 2 atm for 168 hours thermal cycling test (tct) -65c to 150c for 1000 cycles highly accelerated stress test (hast) 130c / 85% rh for 100 hours high temperature stress test (htst) 150c for 1000 hours board level temperature -40c to 125c for 1000 cycles with no failures (for board thickness <40mils and underfilled csp) drop 1m height with no failures 4.2.4. csp carrier information the devices will be provided in standard 7? tape & reel carrier with 5,000 parts per reel. note: all dimensions in millimeters figure 8: csp tape dimensions 4.2.5. csp design considerations in order to achieve the highest level of miniaturization, the c sp package is constrained in ways that will factor into design d ecisions. the csp will only operate in hv mode, and therefore requires a 1.8v oper ating voltage. the number of pins is reduced to 40 (compared to 49 active pins on the qfn). this reduction eliminates access to gpios (0,1,2,6,15), lsad 2, the i2s interface, and the ir remote receiver. for pcb manufacture with belasigna 200 csp, on semiconductor recommends solder-on-pad (sop) surface finish. with sop, the solder mask opening should be solder mask-defined and copper p ad geometry will be dictated by the pcb vendor?s design requirements. rev. 16 | page 13 of 43 | www.onsemi.com
belasigna 200 alternative surface finishes are enig and osp; volume of screened solder paste (#5) should be less than 0.0008mm^3. if no pre- screening of solder paste is used, t hen following conditions must be met: (i) the solder mask opening should be >0.3mm in diameter, (ii) the copper pad will have 0.25mm diameter, and (iii) soldermask thickness should be less than 1mil thick above the copper surface. on semiconductor can provide belasigna 200 csp landpatte rn cad files to assist your pcb design upon request. rev. 16 | page 14 of 43 | www.onsemi.com
belasigna 200 5.0 development tools 5.1 evaluation and development kit (edk) belasigna 200 is supported by a set of development tools included in the evaluation and development kit (edk). the edk is intended for use by dsp software developers and hardwa re systems integrators. it cons ists of the following component s: ? hardware ? belasigna 200 evaluation and development board (contains belasigna 200 device) ? software ? complete assembly to ol chain (assembler, lin ker, librarian, etc.) ? low-level hardware-specific libraries ? basic algorithm toolkit (bat) ? basic operating system libraries (bos) ? wola windows and microcode ? real-time debugger ? eeprom file system manager ? ultraedit ide ? wola toolbox for matlab for rapid ap plication development and prototyping bat and bos provide all the common processing routines in an easy -to-call macro structure. this streamlines the assembly level coding by encapsulating redundant work, while maintaining the true efficiency of hardware-level coding. for advanced dsp developers or application developers, on semi conductor provides an application development extension to the edk, which contains the following: ? python language installer (version 2.2) ? the wxpython gui toolkit ? embedding toolkit (used to build standalone python applications) ? on semiconductor extension ? python interface (pyllcom) to on semiconductor?s low-level communications library (llcom) ? file i/o library (supports standard on semiconductor file formats) ? eeprom access library ? dsh (on semiconductor python shell ? standard command-line shell with customizations for belasigna 200) 5.2 belasigna 200 rapid prototyping module the rapid prototyping module (rpm) is fast and easy for designers to integrate with existing and fu ture products that are not y et dsp- enabled. it also allows for the quick implementation of field tr ials and rapid prototyping to evaluate the benefits of belasign a 200. the rpm features belasigna 200 along with a 256- kbit eeprom for storing a variety of custom algorithms. on-board power regulation circuitry allows the rpm to run off a wide variety of power supp lies. a fast oscillator (included on the rpm) running at 24.576 mhz provides a choice of many sampling frequencies and can be enabled for when heavy-duty signal processing is required. 5.3 belasigna 200 demonstrator the belasigna 200 demonstrator lets device manufacturers quickly and easily assess the speech- and audio-centric benefits deliv ered by belasigna 200 in a full-featured, self -contained portable unit. the demonstrator is housed in a durable, portable, lightweight package complete with belt clip to facilitate dem onstrations in the field. this tool can be easily utilized in real world scenarios to experience the benefits of noise reduction, signal enhanc ement and a variety of other algorithms. th e demonstrator can be connected to a wired headset and function like a dongle to communicate with a bluetooth mobile phone. contact your account mana ger for more information. rev. 16 | page 15 of 43 | www.onsemi.com
belasigna 200 6.0 architecture overview 6.1 rcore dsp the rcore is a 16-bit fixed-point, dual-harvard-architecture d sp. it includes efficient normalize and de-normalize instructions , plus support for double-precision operations to provide the additional dynamic range needed for many applications. all memory locati ons in the system are accessible by the rcore using several addressing modes including indirect and circular modes. the rcore generall y assumes master functionality of the system. 6.1.1. rcore dsp architecture figure 9: rcore programming model ah x mu ph pl st alu exp ae al limiter barrel shifter imm/simm pc y 01p lc lc re pcu ctrl internal router internal router xram yram x_agu pcfg0 pcfg1 pcfg2 r0 r1 r2 r3 y_agu pcfg4 pcfg5 pcfg6 r4 r5 r6 r7 y_bus x_bus pram p_bus d_sys_ctrl d_int_ebl d_aux_reg0 d_aux_reg4 ext3 d_int_status dcu data registers the rcore is a single-cycle pipelined multiply-accumulate (mac) ar chitecture that feeds into a 40 -bit accumulator complete with barrel shifter for fast normalization and de-normalization operations. progr am execution is controlled by a sequencer that employs a t hree- stage pipeline (fetch, decode, execute). furt hermore, the rcore incorporates pointer configuration registers for low cycle-coun t address generation when accessing the three memories: program memory (pram), x data memory (xram) and y data memory (yram). rev. 16 | page 16 of 43 | www.onsemi.com
belasigna 200 6.1.2. instruction set the rcore instruction set can be divided into the following three classes: 1. arithmetic and logic instructions the rcore uses two's complement fractional as a native data forma t. thus, the range of valid numbers is [-1; 1), which is repre sented by 0x8000 to 0x7fff. other formats can be utilized by applying appropriat e shifts to the data. the multiplier takes 16-bit values and performs a multiplication every time an operand is loaded into either the x or y registe r. a number of instructions that allow loading of x and y simultaneously and addition of the new product to the previous product (a mac operation), are available. single-cycle mac wi th data pointer update and fetch is supported. the arithmetic logic unit (alu) receives it s input from either the accumpulator (ae|ah |al) or the product register (ph|pl). alt hough the rcore is a 16-bit system, 32-bit additions or subtractions are also supported. bit manipulation is also available on the accumu lator as well as operations to perform arithmetic or logic shifts, toggling of specific bits, limiting, and other functions. 2. data movement instructions data movement instructions transfer data between ram, control registers and the rcore?s internal registers (accumulator, ph, pl , etc). two address generators are available to simu ltaneously generate two addresses in a single cycle. the address pointers r0..2 and r4..6 can be configured to support increment, decrement, add-by-o ffset, and two types of modulo-n circular buffer operations. s ingle- cycle access to low x memory or low y memory as well as two- cycle instructions for immediate access to any address are also available. 3. program flow control instructions the rcore supports repeating of both single-word instructions and larger segments of code using dedicated repeat instructions o r hardware loop counters. furthermore, instructions to manipulate th e program counter (pc) register such as calls to subroutines, conditional branches and unconditio nal branches are also provided. rev. 16 | page 17 of 43 | www.onsemi.com
belasigna 200 7.0 instruction set table 6: instruction set instruction description instruction description abs a [,cond] [,dw] calculate absolute value of a on condition dcmp compare ph | pl to a add a, reg [,c] add register to a dec a [,cond] [,dw] decrement a on condition add a, (rij) [,c] add memory to a dec reg [cond] decrement register on condition add a, dram [,b] add (dram) to a dec (rij) [,cond] decrement memory on condition add a, (rij)p [,c] add program memory to a dsub [cond] [,p] subtract ph | pl from a, update ph | pl on condition add a, rc [,c] add rc register to a eor a, reg exclusive-or register with ah to ah addi a, imm [,c] add imm to a eor a, (r ij) exclusive-or memory with ah to ah adsi a, simm add signed simm to a eor a, dram [,b] exclusive-or (dram) with ah to ah and a, reg and register with ah to ah eor a, (rij)p exclusive-or program memory with ah to ah and a, (rij) and memory with ah to ah eor a, rc exclusive-or rc register with ah to ah and a, dram [,b] and (dram) with ah to ah eori a, imm exclusive-or imm with ah to ah and a, (rij)p and program memory with ah to ah eosi a, simm exclusive-or unsigned simm with ah to ah and a, rc and rc register with ah to ah inc a [,cond] [,dw] increment a on condition andi a, imm and imm with ah to ah inc reg [,cond] increment register on condition ansi a, simm and unsigned simm with ah to ah inc (rij) [,cond] increment memory on condition bra pram [,cond] branch to new address on condition ld rc, rc load rc register with rc register break stop the dsp for debugging purposes ld reg, reg load register with register call pram [,cond] [,b] push pc and branch to new address on condition ld reg, (rij) load register with memory clb a calculate the leading bits on a ld (rij), reg load memory with register clr a [,dw] clear accumulator ld a, dram [,b] load a with (dram) clr reg clear register ld dram, a [,b] load (dram) with a cmp a, reg [,c] compare register to a ld rc, (rij) load rc register with memory cmp a, (rij) [,c] compare memory to a ld (rij), rc load memory with rc register cmp a, dram [,b] compare (dram) to a ld reg, (rij)p load register with program memory cmp a, (rij)p [,c] compare program memory to a ld (rij)p, reg load program memory with register cmp a, rc [,c] compare rc register to a ld reg, (reg)p load register with program memory via register cmpi a, imm [,c] compare imm to a ld reg, rc load register with rc register cmsi a, simm compare signed simm to a ld rc, reg load rc register with register cmpl a [,cond] [,dw] calculate logical inverse of a on condition ldi reg, imm load register with imm dadd [cond] [,p] add ph | pl to a, update ph | pl on condition ldi rc, imm load rc register with imm dbnz0/1 pram branch to new address if lc0/1 <> 0 ldi (rij), imm load memory with imm rev. 16 | page 18 of 43 | www.onsemi.com
belasigna 200 table 7: instruction set continued instruction description instruction description ldlc0/1 simm load loop counter with 8-bit unsigned simm push imm [,b] push imm on stack ldsi a, simm load a with signed simm rep n repeat next instruction n+1 times (9-bit unsigned) ldsi rij, simm load pointer register with unsigned simm rep reg repeat next instruction reg+1 times mld (rj), (ri) [,sq] multiplier load and clear a rep (rij) repeat next instruction (rij)+1 times mld reg, (ri) [,sq] multiplier load and clear a res reg, bit clear bit in register modr rj, ri pointer register modification res (rij), bit clear bit in memory mpya (rj), (ri) [,sq] multiplier load and accumulate ret [b] return from subroutine mpya reg, (ri) [,sq] multiplier load and accumulate rnd a round a with al mpys (rj), (ri) [,sq] multiplier load and accumulate negative set reg, bit set bit in register mpys reg, (ri) [,sq] multiplier load and accumulate negative set (rij), bit set bit in memory mset (rj), (ri) [,sq] multiplier l oad set_ie set interrupt enable flag mset reg, (ri) [,sq] multiplier load shft n shift a by +/- n bits (6-bit signed) mul [cond] [,a] [,p] update a and/or ph | pl with x*y on condition shft a [,cond] [,inv] shift a by exp bits on condition neg a [,cond] [,dw] calculate negative value of a on condition sleep [ie] sleep nop no operation sub a, reg [,c] subtract register from a or a, reg or register with ah to ah sub a, (rij) [,c] subtract memory from a or a, (rij) or memory with ah to ah sub a, dram [,b] subtract (dram) from a or a, dram [,b] or (dram) with ah to ah sub a, (rij)p [,c] subtract program memory from a or a, (rij)p or program memory with ah to ah sub a, rc [,c] subtract rc register from a or a, rc or rc register with ah to ah subi a, imm [,c] subtract imm from a ori a, imm or imm with ah to ah susi a, simm subtract signed simm from a orsi a, simm or unsigned simm with ah to ah swap a [,cond] swap ah, al on condition pop reg [,b] pop register from stack tgl reg, bit toggle bit in register pop rc [,b] pop rc register from stack tgl (rij), bit toggle bit in memory push reg [,b] push register on stack tst reg, bit test bit in register push rc [,b] push rc register on stack tst (rij), bit test bit in memory table 8: notation symbol meaning symbol meaning a b accumulator update memory bank selection (x or y) inv inverse shift c carry bit p pram ph | pl update program memory address (16 bits) cond condition in status register rc rc r egister (r0..7, pcfg0..2, pcfg4..6, lc0/1) dram low data (x or y) memory address (8 bits) reg data register (al, ah, x, y, st, pc, pl, ph, ext0, exp, ae, ext3..ext7) dw double word ri / rj / rij pointer to x / y / either data memory ie interrupt enable flag simm short immediate data (10 bits) imm immediate data (16 bits) sq square rev. 16 | page 19 of 43 | www.onsemi.com
belasigna 200 7.1 weighted overlap-add (wola) filterbank coprocessor the wola coprocessor performs low-delay, high-fidelity filterbank processing to prov ide efficient time-frequency processing. th e coprocessor stores intermediate data values, program code and window coefficients in its own memory space. audio data are accessed directly from the input and output fifos where they are automatically managed by the iop. the wola coprocessor can be configured to handle different sizes and types of transforms, such as mono, simple stereo or full s tereo configurations. the number of bands, the st acking mode (even or odd), the oversampling factor, and the shape of the analysis an d synthesis windows used are all configurable. the selected set of parameters affects both the frequency resolution, the group de lay through the wola coprocessor and the number of cycles needed for complete execution. the wola coprocessor can generat e both real and complex data. eit her real or complex gains can be applied. the rcore always has access to these values through shared memories. all parameters ar e configurable with microcode, which is used to control the wo la during execution. the rcore initiates all wola functions (analysis, gain applicati ons, synthesis) through dedicated control registers. a dedicate d interrupt is used to signal completion of a wola function. many standard wola microcode configurations are delivered with the edk. these confi gurations have been specially designed for l ow group delay and high fidelity. 7.2 input output processor (iop) the iop is an audio-optimized configurable dma unit for audio data samples. it manages the collection of data from the a/d conv erters to the input fifo and feeds digital data to the audio output st age from the output fifo. the iop can be configured to access da ta in the fifos in four different ways: ? mono mode: input samples are stored sequentially in the input fifo. ou tput samples are stored sequentially in the output fifo. ? simple stereo mode: input samples from the two channels are stored interleaved in the input fifo. output samples for the single output channel are stored in the lower part of the output fifo. ? digital mixed mode: input samples from the two channels are stored in each half of the input fifo. output samples for the single output channel are stored in the lower half of the output fifo. ? full stereo mode: input samples from the two channels are stored interleaved in the input fifo. output samples for the two output channels are stored interleaved in the output fifo. (note: a one-in, two-out configurat ion can be achieved in this mode by leav ing the second input unused). figure 10: four audio modes rev. 16 | page 20 of 43 | www.onsemi.com
belasigna 200 the iop places and retrieves fifo data in memories shared with th e rcore. each fifo (input and ou tput) has two memory interface s. the first corresponds with the normal fifo. here the address of the most recent inpu t block changes as new blocks arrive. the s econd corresponds with the smart fifo. in this scheme the address of the most recent input block is fixed. the smart fifo interface i s especially useful for time-domain filters. in the case where the wola and the iop no longer work together as a result of a low battery condition, an iop end-of-battery-li fe auto- mute feature is available. 7.3 general-purpose timer the general-purpose timer is a 12-bit countdown timer with a 3-bi t prescaler that interrupts the rcore when it reaches zero. it can operate in two modes, single-shot or continuous. in single-shot mode the timer counts down only once and then generates an inte rrupt. it will then have to be restarted from the rcore. in continuous mode the timer restarts with full timeout setting every time it hits zero and interrupts are generated co ntinuously. this unit is often useful in scheduli ng tasks that are not part of the sample-based sign al processing scheme, such as checking a battery volta ge, or reading the value of a volume control. 7.4 watchdog timer the watchdog timer is a configurable hardware timer that operates from the system clock and is used to prevent unexpected or unstable system states. it is always active and must be periodical ly acknowledged as a check that an application is still runni ng. once the watchdog times out, it generates an interrupt. if left to time out a second consecutive time without acknowledgement, a sys tem reset will occur. 7.5 ram and rom there are 20 kwords of on-chip program and data ram on belasig na 200. these are divided into three entities: a 12-kword program memory, and two 4-kword data memories ("x" and "y" as are common in a dual-harvard architecture). there are also three ram banks that are sh ared between the rcore and wola coprocessor. these memory banks contain the input and output fifos, gain tables for the wola coprocessor, temporary memory for wola ca lculations, wola coprocessor results, and the wola coprocessor microcode. there is a 128-word lookup tabl e (lut) rom that contains log 2 (x), 2 x , 1/x and sqrt(x) values, and a 1-kw ord programrom that is used during booting and configur ation of the system. complete memory maps for belasigna 200 are shown in figure 11 . rev. 16 | page 21 of 43 | www.onsemi.com
belasigna 200 figure 11: memory maps 7.6 interrupts the rcore dsp has a single interrupt channel that serves eleven interrupt sources in a prioritized manner. the interrupt contro ller also handles interrupt acknowledge flags. every interrupt source has its own interrupt vector. furthermore, the priority scheme of t he interrupt sources can be modified. refer to table 9 for a description of all the interrupts. rev. 16 | page 22 of 43 | www.onsemi.com
belasigna 200 table 9: interrupts interrupt description wola_done wola function done io_block_full iop interrupt pcm pcm interface interrupt uart_rx general-purpose uart receive interrupt uart_tx general-purpose uart transmit interrupt gp_timer general-purpose timer interrupt watchdog_timer watchdog timer interrupt spi_interface spi interface interrupt twss_interface twss interface interrupt ext3_rx ext3 register receive interrupt ext3_tx ext3 register transmit interrupt rev. 16 | page 23 of 43 | www.onsemi.com
belasigna 200 8.0 description of analog blocks 8.1 input stage the analog audio input stage is comprised of two individual channe ls. for each channel, one of two possible inputs is routed to the input of the programmable preamplifier t hat can be configured for bypass or gain values of 12 to 30db (3-db steps). the analog signal is filtered to remove frequencies above 10khz before it is passed into the high-fidelity 16-bit oversampling ? a/d converter. subsequently, any necessary sample rate decimation is performed to downsample the signal to the desired sampling rat e. during decimation the level of the signal can be adjusted digitally for optimal gain matching between the two input channels. a ny undesired dc component can be removed by a configurable dc-remova l filter that is part of the decimation circuitry. the dc remo val filter can be bypassed or configured for cut-off frequencies at 5, 10 and 20hz. a built-in feature allows a sampling delay to be configured betwe en channel zero and channel one. this is useful in beam-formin g applications. for power consumption savings either of the input channels can be disabled via software. figure 12: input stage 8.2 output stage the analog audio output stage is composed of two individual chan nels. the first part of the output stage interpolates the signa l for highly oversampled d/a conversion and automatically configures itself for the desired oversampling rate. here, the signal is ro uted to both the ? d/a converter and the direct digital outputs. the d/a converter translates the signal into a high-fidelity analog signal and passes it into a reconstruction filter to smooth out the effects of sampling. the re construction filter has a fixed cut-off fre quency at 10khz. from the reconstruction filter, the signa l passes through the programmable output attenuator, which can adjust the signal for v arious line-level outputs or mute the signal altogether. the attenuator ca n be bypassed or configured to a value in the interval -12 t o -30db (3- db steps). the direct digital output provides a bridge driven by a pulse-d ensity modulated output that can be used to directly drive an ou tput transducer without the need for an external power amplifier. rev. 16 | page 24 of 43 | www.onsemi.com
belasigna 200 two analog outputs designed to drive exte rnal amplifiers are also available. figure 13: output stage 8.3 clock-generation circuitry belasigna 200 operates with two main clock domains: a domain ru nning on the system clock (sys_clk) and a domain running on the main clock (mclk). sys_clk can either be in ternally generated or externally delivered. it is used to drive all on-chip processo rs such as the rcore, the wola coprocessor and the iop. mclk is generated by division of sys_clk and is used to drive all a/d converter s, d/a converters and external interfaces (except spi, pcm, i 2 s, and gpio interfaces). the division factor used to create the desired mclk from sys_clk is configurable to support external clocks with a wide range of frequencies. the sampling frequency of all a/d converte rs and d/a converters also depends on mc lk. when mclk is 1.28mhz, sampling frequencies in the interval 10.7khz to 20khz can be selected. sampling frequencies up to 60khz can be obtained with other mclk frequencies. 8.4 battery monitor a programmable on-chip battery monitor is available for power management. the battery monitor works by incrementing a counter value every time the battery voltage goes below a desired, configurable threshold valu e. this counter value can be used in an application-specific power-ma nagement algorithm running on the rcore. the rcore can in itiate any desired ac tions in case the ba ttery hits a predetermined value. 8.5 multi-chip sample clock synchronization belasigna 200 allows mclk synchronization between two or more belasigna 200 chips connected in a multi-chip configuration. samples on multiple chips occur at the same instant in time. this is useful in applications us ing microphone arrays where synch ronous sampling is required. the sample clock synchronization is enabl ed using a control bit and a gpio assignment that brings all mcl ks across chips to zero phase at the same instant in time. rev. 16 | page 25 of 43 | www.onsemi.com
belasigna 200 9.0 external interfaces 9.1 external digital interfaces 9.1.1. pulse-code modulation interface (pcm i/f) the pcm interface is a bi-directional, four-wire synchronous seri al interface suitable for high-speed digital audio transfer. t his externally-clocked interface is capable of sending data serially at rates up to the clock speed of the rcore, providing the nec essary bandwidth for digital audio. this interface can also be used for a number of other functions, including multi-processing belasi gna 200 chips. the interface is configurable for glueless connections to four-wire pcm interfaces as well as other belasigna 200 chips in a belasigna 200 multi-chip configuration. both master and slave modes are supported. the interface is configured via a memory-map ped configuration register and interacts with the rcore through me mory-mapped control registers and interrupts. refer to section 12.1 for timing specifications. 9.1.2. general-purpose input/output (gpio) up to 16 gpio pins are available to be configured as inputs or as outputs. all gpio pins are pulled up internally. data are rea d or written via a memory-mapped control register. gpio pins can be used to interface to digital switches, other devices, etc. the d irection of each bit is programmable via a direction register. refer to section 12.2 for timing specifications. 9.1.3. serial peripheral interface (spi) port the spi port allows belasigna 200 to communicate synchronously with other devices such as external memory or eeprom. this spi interface conforms to the standard spi bus protocol supporting modes zero and two as a master, and transfer speeds up to half t he system clock frequency. the interface is configured via a memory -mapped configuration register and interacts with the rcore thr ough memory-mapped control registers and interrupts. refer to section 12.3 for timing specifications. 9.1.4. rs-232 universal asynchronous receiver/transmitter (uart) the general-purpose uart is a low-voltage rs-232-compatible interf ace. all data are transmitted and received with eight data bi ts, no parity and one stop bit (8n1). a range of st andard data rates, up to a maximum of 115.2k bps, is supported. the interface is con figured via a memory-mapped configuration register and interacts with the rcore through memory-mapped control registers and interrupts. 9.1.5. debug port the debug port is also a low-voltage rs-232-based uart, and it inte rfaces directly to the program controller. this interface di ffers from the general-purpose uart in its access path to the rcore. it is used primarily by the evaluation and development tools to inter face to, program and debug belasigna 200 applications. data rates up to 115.2kbps are supported. the protocol uses eight data bits, no p arity and one stop bit (8n1). 9.1.6. two-wire synchronous serial (twss) interface this industry standard two-wire high-speed synchronous serial inte rface allows communication to a variety of other integrated c ircuits and memories. on belasigna 200, this interface operates in slav e mode only. data rates up to 400kbps are supported for mclk frequencies higher than 1.28mhz; for lower mclk frequencies, the maxi mum rate is 100kbps. the interface is configured via memor y mapped configuration registers and interacts with the rcore through memory-mapped cont rol registers and interrupts. the twss interface is compatible with the philips' i 2 c protocol. 9.1.7. i 2 s interface this industry standard digital audio interface uses a three-wire serial protocol to transmit and receive audio between belasign a 200 and other systems. the interface o perates at the system clock frequency and belasi gna 200 always assumes master functionality. rev. 16 | page 26 of 43 | www.onsemi.com
belasigna 200 9.2 external analog interfaces 9.2.1. low-speed a/d converters (lsad) six lsad inputs are available on belasigna 200. combined with two internal lsad inputs (supply and ground) this gives a total o f eight multiplexed inputs to the lsad converter. the multiplexed inputs are sampled sequentia lly at 1.6khz per c hannel. the native dat a format for the lsad is 10-bit two's comple ment. however, a total of eight operation mo des are provided that allow a configurabl e input dynamic range in cases where certain minimum and maximum values for the converted inputs are desired; such as in the case of a volume control where only input values up to a certain magnitude are allowed. rev. 16 | page 27 of 43 | www.onsemi.com
belasigna 200 10.0 boot sequence belasigna 200 boots in a two-stage boot seque nce. the programrom begins loading the bootloader from an external spi eeprom 200ms after power is applied to the chip. in this process the programrom checks the eeprom file structure to ensure validity. i f the file structure is validated, the bootloader is written to pram. in case of an error while reading the external eeprom, all outp uts are muted. the system will then reset due to a watchdog timeout. once the bootloader is loaded into pram the program counter is set to point to the beginning of the bootloader code. subsequent ly, the signal-processing application that is stored in the eeprom is downloaded to pram by the bootloader. the boot process genera lly takes less than one second. on semiconductor provides a standard full-featured bootloader. an alternative to bootloading is often used in development - program code can be loaded through the debug port after powering belasigna 200. in this case, an spi eeprom may or may not be a ttached, and the debug port takes over control of the system. som e products use this technique when an eeprom is not suitable to the application. rev. 16 | page 28 of 43 | www.onsemi.com
belasigna 200 11.0 electrical characteristics 11.1 absolute maximum ratings table 10: absolute maximum ratings parameter min. max. unit supply voltage 2.0 v operating temperature range 2 -40 85 c storage temperature range -55 125 c voltage at any input pin -0.3 2.1 v caution: class 2 esd sensit ivity, jesd22-a114-b (2000v) 11.2 electrical characteristics conditions: temperature = 25c, f sys_clk = 1.28mhz (internal), f mclk = 1.28mhz, f samp = 16khz, v bat = 1.8v table 11: electrical characteristics parameter symbol conditions min. typ. max. unit overall (1f vbat external capacitor) supply voltage vbat 1.0 3 1.25 1.8 v current consumption 4 ibat vbat = 1.8v 650 a vreg (1f external capacitor) regulated output vreg unloaded 0.9 1.0 1.1 v psrr @ 1khz 35 50 db load current ireg 2 ma load regulation 12 18 mv/ma line regulation 2 5 mv/v vdbl (1f external capacitor) regulated output vdbl 1.8 2.0 2.2 v psrr @ 1khz 45 db load current ireg 2 ma load regulation charge pump cap = 100nf 130 200 mv/ma line regulation 5 8 mv/v vddc (1f external capacitor) hv output hv hv mode vbat v 2 audio performance parameters may degrade outside the range of 0 to 70 degrees c. internal oscillator speed will vary with temp erature 3 device will operate down to 0.9v bu t with degraded system specifications 4 dsp core active; single channel; direct di gital output enabled and connected to 100k resistance rev. 16 | page 29 of 43 | www.onsemi.com
belasigna 200 11.3 analog characteristics conditions: temperature = 25c, f sys_clk = 1.28mhz (internal), f mclk = 1.28mhz, f samp = 16khz, v bat = 1.8v table 12: analog characteristics parameter symbol conditions min. typ. max. unit input stage input voltage vin ai0, ai1, ai2, ai3 inputs 0db preamp gain -1 1 vp input impedance 5 rin preamplifier gain 12, 15, 18, 21, 24, 27, 30db 385 550 715 k? input referred noise irn unweighted, 20hz to 8khz bw, 30db preamp gain 3 vrms input dynamic range unweighted, 20hz to 8khz bw, 0db preamp gain 85 db input thd+n unweighted, 20hz to 8khz bw, 0db preamp gain, input at 1 khz -60 db preamplifier gain tolerance (0, 12, 15, 18, 21, 24, 27, 30db) 50% re. fs input at 1khz -1.5 1.5 db output stage line out output level vlo ai1 -1 1 vp line out output impedance rlo ai1 5 k? output impedance 6 rao ao0. attenuator = 12, 15, 18, 21, 24, 27, 30db 8.9 12.8 16.6 k ? output dynamic range unweighted, 100hz to 22khz bw, 0db output attenuation 75 db output thd+n unweighted, 100hz to 22khz bw, 0db output attenuation, input at 1khz -60 db output attenuator tolerance (0,12,15,18,21,24,27,30db) 50% re. fs input at 1khz -2 2 db low-speed a/d input voltage peak input volt age, hv mode -0.3 2.1 v sampling frequency all channels sequentially mclk = 1.28mhz 12.8 khz channel frequency 8 channels 1.6 khz anti-aliasing filters (input and output) cut-off frequencies 7 10 13 khz passband flatness -1 1 db stopband attenuation 80 db 5 depends slightly on the preamp gain 6 depends strongly on the attenuator rev. 16 | page 30 of 43 | www.onsemi.com
belasigna 200 11.4 digital characteristics conditions: temperature = 25c, f sys_clk = 1.28mhz (internal), f mclk = 1.28mhz, f samp = 16khz, v bat = 1.8v table 13: digital characteristics parameter symbol conditions min. typ. max. unit output stage direct digital output load current ido 25 ma direct digital output resistance rdo 10 20 ? direct digital output 0 dynamic range unweighted, 100hz to 22khz bw 77 db direct digital output 0 thd+n unweighted, 100hz to 10khz bw input at 1khz -63 db direct digital output 1 dynamic range unweighted, 100hz to 22khz bw 75 db direct digital output 1 thd+n unweighted, 100hz to 10khz bw input at 1khz -62 db internal oscillator characteristics clock frequency (internal) f sys_clk 1.28 mhz oscillator jitter 0.4 1.0 ns oscillator start-up voltage 0.55 0.7 0.85 v oscillator settling time time required for frequency change of 20% 1 ms other clock frequency (external) f sys_clk hv mode 33 mhz high-level input voltage vih 7 1.45 1.8 2.0 v low-level input voltage vil 7 0 0.35 v high-level output voltage rout = 50ohm voh 7 isource = 1ma 1.45 1.8 v low-level output voltage rout = 50ohm vol isink = 1ma 0.05 0.1 v input capacitance (digital i/o pads) cin 5 pf output capacitance (digital i/o pads) cout maximum load 100 pf pull-up resistors rup 215 430 645 k ? pull-down resistors rdown 215 430 645 k? 7 digital low (0) represented below 20% of vbat. digital high (1) represented above 80% of vbat. rev. 16 | page 31 of 43 | www.onsemi.com
belasigna 200 12.0 timing diagrams 12.1 pcm interface timing diagrams 12.1.1. 16-bit figure 14: lsb advanced short figure 15: lsb advanced wide rev. 16 | page 32 of 43 | www.onsemi.com
belasigna 200 figure 16: lsb del short figure 17: lsb del wide rev. 16 | page 33 of 43 | www.onsemi.com
belasigna 200 figure 18: msb advanced short figure 19: msb advanced wide rev. 16 | page 34 of 43 | www.onsemi.com
belasigna 200 figure 20: msb del short figure 21: msb del wide rev. 16 | page 35 of 43 | www.onsemi.com
belasigna 200 12.1.2. 32-bit figure 22: lsb advanced short figure 23: lsb advanced wide rev. 16 | page 36 of 43 | www.onsemi.com
belasigna 200 figure 24: lsb del short figure 25: lsb del wide rev. 16 | page 37 of 43 | www.onsemi.com
belasigna 200 figure 26: msb advanced short figure 27: msb advanced wide rev. 16 | page 38 of 43 | www.onsemi.com
belasigna 200 figure 28: msb del short figure 29: msb del wide table 14: pcm inter ons face descripti parameter description min. max. unit t dv pcm_clk high to data valid 50 ns t s setup time before pcm_clk high 10 ns t fr pcm_clk high to pcm_frame hi gh 50 ns t ch pcm_clk high period (1.28mhz) 390 ns t cl pcm_clk low period (1.28mhz) 390 ns rev. 16 | page 39 of 43 | www.onsemi.com
belasigna 200 12.2 gpio timing diagram figure 30: gpio timing diagram table 15: gpio interface descriptions parameter description min. max. unit t dv sys_clk high to data valid 50 ns t s setup time before sys_clk high 10 ns t ch sys_clk high period (1.28mhz) 390 ns t cl sys_clk low period (1.28mhz) 390 ns rev. 16 | page 40 of 43 | www.onsemi.com
belasigna 200 12.3 spi port timing diagram figure 31: spi port timing diagram table 16: spi interface descriptions parameter description min. max. unit t dv spi_clk high to output data valid 50 ns t s setup time before spi_clk high 10 ns t fce spi_cs low to first spi_clk high ns rev. 16 | page 41 of 43 | www.onsemi.com
belasigna 200 13.0 re-flow information the re-flow profile depends on the equipment t hat is used for the reflow and the assemb ly that is being reflowed. use the follo wing table from the jedec standard 22-a113d para 3.1.6 for sn-pb eutectic assembly as a guideline: table 17: re-flow information profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tl to tp) 3c/second maximum 3c/second maximum preheat temperature minimum (tsmin) 100c 150c temperature maximum (tsmax) 150c 200c time (min. to max.) (ts) 60-120 seconds 60-180 seconds tsmax to tl ramp-up rate 3c/second maximum time maintained above temperature (tl) 183c 217c time (tl) 60-150 seconds 60-150 seconds peak temperature (tp) 240 +0/-5c 260 +0/-5c time within 5c of actual peak temperature 10-30 seconds 10-30 seconds ramp-down rate 6c/second maximum 6c/second maximum time 25c to peak temperature 6 minutes maximum 8 minutes maximum all belasigna 200 qfns with part number revisions 003 (i.e. 0w344- 003-xtp) and higher are pb-free and should follow the re-flow guidelines for pb-free assemblies. al l belasigna 200 csps are pb-free. 14.0 esd sensitive device caution: electrostatic discharge (esd) sensitive device. pe rmanent damage may occur on devices subjected to high-energy electrostatic discharges. proper esd precautions in handling, packaging and testing are recommended to avoid performance degr adation or loss of functionality. 15.0 training to facilitate development on the belasigna 200 platform, training is available upon request. contact your account manager for m ore information. rev. 16 | page 42 of 43 | www.onsemi.com
rev. 16 | page 43 of 43 | www.onsemi.com belasigna 200 16.0 ordering information part number package shipping configuration temperature range 0W344-004-XTP 8x8mm qfn tape & reel (500 parts per reel) -85 to 40 c 0w344-005-xtp 8x8mm qfn tape & reel (1000 parts per reel) -85 to 40 c 0w588-002-xua 2.3x2.8mm wlcsp tape & reel (5000 parts per reel) -85 to 40 c 17.0 company or product inquiries for more information ab out on semiconductor?s products or services visit our web site at http://onsemi.com . on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regardin g the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal op portunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-3 -3867 toll free usa/canada 44 email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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